What is the HW requirement for one instance of ISPC? Does it require one ALU and one execution context? In other words, can a core with two ALUs and one execution context run two ISPC instances?

I think so @suninhouse

An entire gang of program instances is compiled to a sequence of vector instructions that is executed by one hardware thread in a modern CPU core.

I think @kayvonf's comment implies that one ALU is not going to be sufficient to run programs compiled by ISPC because it needs to have the capability to execute vector operations. @sininhouse @ufxela

Oops @suninhouse sorry

I think uniform is also used for performance improvement in ispc to indicate that the value is shared among all program instances and it usually just correspond to a simple load like in the example.

I had a this question in lecture but it went unanswered. If each gang of program instances is mapped to SIMD instructions, is the size of a gang limited by the width of SIMD vectors?

@l-henken the size of the gang should not be limited by width of SIMD vector as an abstraction. Rather, the percentage of active instructions in the gang should be determined by width of SIMD.