One thing I've been wondering about the ts instruction is how it's operation is guaranteed when within a pipelined processor since many instructions will be running at different stages of the pipeline concurrently. Would conflict signals just be used within the pipeline in order to prevent concurrent memory accesses?

@swkonz I might be wrong, but I was under the impression that instructions like ts that the hardware guarantees to be atomic would disrupt (and monopolize) the CPU pipeline in order to guarantee atomicity, which is part of why such instructions are so expensive and you have to pay a premium for locking and unlocking.