Xilinx provides users with API that can directly program FPGA's LUTs, user can use ICAP (internal configuration access port) or PCAP (processor configuration access port) to access the configuration registers and change the logic functions.

So, my understanding based on what we talked about in lecture is that an FPGA is essentially just a massive interconnected chain of these gates in various orders where we can program the tables therein? Is that correct, or is there more to it?

@harrymellsop yes I think that's correct, a massive configurable interconnect chain of gates. That portion is usually referred to as a CLB (configurable logic block). In addition it also has DSP tiles for signal processing, transceivers for transmitting and receiving serial data, RAM for memory and I/O blocks for data transfers into and out of the FPGA.