Purpose of the padding is to prevent threads from sharing the same cacheline

The extra padding is useful such that each element in the array could be aligned with cache lines, and thus to reduce artificial communications.

Note: we don't pad-by-default because it causes extra memory overhead and seems to be useful mainly when we have many threads doing writes to a shared array. If they instead were doing reads to a shared array, there wouldn't be a need for repeated cache line invalidation.

Is this something we can practically do? Are there intrinsics that we can use to extract the size of a cache line?

@harrymellsop Yes, this can be practically done. I'm not aware of any intrinsics, but the size of a cacheline is usually specified in the architecture of the CPU. Typically what engineers do is look it up(online or in the chip manual) and design their programs based on that reference. So yes you can practically do this. In fact a common practice for testing the coherency of multicore systems is to implement false sharing where multiple cores, load and store to different indices of an array that fits in one cacheline.