Is the slower critical section also a result of bus contention, where the critical section's memory access are slowed down? Would a critical section using only variables in registers be affected?

The critical section slows down because it also wants to write to cache or memory but the bus is full of interconnected traffic (or invalidating lines) of other waiting processors.

Is there a good explanation for the irregularity of the graph? It does seem somewhat linear, but the deviations, especially at 4 and 5, seem very large. Maybe something specific to how the bus is implemented at those sizes?