P1 holds the lock the entire time the other processors are spinning and unlocks after updating the desired cache line.

P1's cache contains a valid copy of the cache line containing the lock variable only after it unlocks. Until then, every processor that issued a RdX had the potential to modify the lock variable (acquire) so the lock in P1's cache line was invalid for the duration of the time it held the lock.

If there's no other processors competing for the lock (i.e. BusRdX not sent after P1 acquires the lock), P1's cacheline for lock will be valid when it has the lock, right?

Although P1 holds the lock for the whole time, it only has a valid cache line at the beginning and at the end.

My understanding is that P1 holds the lock the entire time from when it acquires it to when it releases it, P1's cache only has a valid copy of the lock variable as it is locking and unlocking the lock, not during the majority of the time it holds the lock. This is because in attempting to take the lock using an atomic set instruction, the other threads send a BusRdX inclusive on the bus, which informs all other threads holding the cache line to invalidate their copies, including the copy in P1. This also leads to a large amount of bus traffic, which can slow down the program, as caches are constantly being invalidated.