I am a little bit confused. Suppose that at the beginning, for an address line, all threads except thread 1 are at S state and thread 1 is at I state. And then, thread 1 upgrades to E state. So, at this time, what are the states for other threads after BusRd?

Then, if some threads want to read the memory (E state in thread 1), what are the processors and bus transactions?

MESI is an invalidation protocol that builds upon MSI. It is pretty much the same except that there is a new state E, for exclusive, that a cache line can be in. This Exclusive state means the line has not yet been modified (written to), but it is in the only cache that has a copy of this line. This improves performance because previously in MSI, there were two bus transactions for every read quickly followed by a write to the same address, which is a common occurrence. The first was a read, triggering a BusRd to move from state Invalid to Shared, and the second was a write, triggering a BusRdX to move from Shared to Modified. This Exclusive state is essentially a special case of the Shared state. Instead of being lumped into Shared state which means 1 or more cache lines have this data available read-only, Exclusive state means just 1 cache line is like this.

@Nian I think it's not possible for the cache C servicing thread 1 to upgrade from I to E state, because E state requires that it must be the only cache that has a copy of the line. Once you have other cache's with the same line in S state, the original cache C no longer has "exclusive clean" ownership.

If you go to slide 35, you can see that if that cache line needs to be brought into another cache, then a BusRd request is sent on the bus, which will change the cache line of the previous line (in E-state) and the new line (previously in I-state) both to S-state.

A point made about MSI is that, since processors are sharing data, there are more cache hits and communication costs. MESI helps reduce this issue with the extra E state because there is no need for an extra bus transaction moving from E to M since no other cache has that in its line.

To clarify, a processor doesn't explicitly ask to be put into the shared or exclusive states, right? The bus automatically puts a processor into one of the two states when it performs a read depending on whether or not any other processors are currently reading the same data?

@tp. I'd like you to think of it as each cache controlling its own state by carrying out the state machine defined by the coherence protocol. (See MSI in the previous slides or MESI here.) Changes in state occur when the local processor makes LD/ST requests to the cache, or the cache received coherence messages other caches announcing their own state changes.

In other words, the caches cooperates to maintain memory coherence by independently carrying out the coherence protocol.

Got it, thanks Kayvon