What is a ballpark number for the difference in clock speed and instructions per clock cycle for a core from a multicore architecture vs one designed for a chip doing just single-stream processing? Also do the ISAs differ to better use the more simple multicore units?

@ishangaur I'm not exactly sure but I think we can get a sense of the difference by looking at the difference between base and turbo boost frequencies on different CPUs because, from my understanding, turbo boost will turn off some cores in order to supply more juice to one of them running at a higher clock rate. From (here)[https://geek-computer.com/wiki/base-frequency-vs-turbo-max-frequency] it seems like the Intel Core i7-8750H's base frequency is 2.2 GHz while its turbo boost frequency is 4.1 GHz. Thus, the difference can be at least 1.9 GHz!

In the first lecture we saw how even with twice as much parallelism, the communication cost between two cores can lead to significant overhead. What effect does splitting work across multiple cores and then combining the results have on things like cache locality, if any? More generally, what are some guidelines for writing cache-efficient parallel code?

@danieljm each core has their own L1 cache and cache coherency protocol would guarantee the memory is consistent across all the cores. In cases where a core does not read or write to the same memory region as other cores, you can optimize cache efficiency similar to the usage of a single core; otherwise a deeper understanding of cache coherence is needed to know when the data in cache is invalided/evicted.