reiterating my understanding -- P0 needs to write to P1 and P2 because this piece of data is shared by those two processes at the moment. this will maintain memory coherence between the multiple processors
kayvonf
@bittimecore -- P0 is not "writing" to P1 and P2. P0 wants to write to the memory address X. Like in any invalidation-based coherence protocol, P0 must be the only holder of the line before writing. Therefore, P0 must inform all processors holding a copy of this line in their cache. Once these other processors invalidate the line (no longer hold a copy), P0 can proceed with its write since it now has exclusive access to the line.
reiterating my understanding -- P0 needs to write to P1 and P2 because this piece of data is shared by those two processes at the moment. this will maintain memory coherence between the multiple processors
@bittimecore -- P0 is not "writing" to P1 and P2. P0 wants to write to the memory address X. Like in any invalidation-based coherence protocol, P0 must be the only holder of the line before writing. Therefore, P0 must inform all processors holding a copy of this line in their cache. Once these other processors invalidate the line (no longer hold a copy), P0 can proceed with its write since it now has exclusive access to the line.