In lecture, we went over an animation of the different memory speeds that seemed to show data transferring between the different caches. Is it common that the data on DRAM will move to the L3/L2/L1 caches before being being used by the CPU?
In lecture, we went over an animation of the different memory speeds that seemed to show data transferring between the different caches. Is it common that the data on DRAM will move to the L3/L2/L1 caches before being being used by the CPU?