How do you tell from the figure that the memory bus is fully utilized? There is no waiting period bewteen two sessions of memory loading.

For the last question, I think: Processor stalls will reduce as we increase our arithmetic intensity. Since we'll be doing significantly more arithmetic operations than load, this means the frequency of load operations will significantly reduce. Hence, there would be sufficient time between load operations.

1. Is the answer: You could have multiple loads going at the same time, so blue boxes could overlap?

3*

Higher memory latency would be illustrated by longer blue bars

The processor would not stalls if the ratio of math instructions to load instructions was significantly increased. The graph in the previous slide hint that the CPU can smartly issue a load instruction a few clock cycles earlier before it is actually needed in computation and continue to work on math at current context. Therefore the math and transfer can happen concurrently and therefore no stall.

1 Memory bus is fully utilized because if we plot the memory bus occupancy vs time there are no gaps. 2 The blue bars would become longer. 3 We can overlap the blue boxes for a given time slice up to bandwidth. 4 No because we can fill the processor with math instructions while waiting for the load to complete.