Regarding the last question, in a cache coherent processor, the LL operation would cause the cache line x is in to be loaded and is changed to S state. The SC instruction could then only issue BusRdX to change the line to M state so it can store value to x if the line was in S state.

If the line were in I state, it's a little complicated as it depends on what is on that cache line. If x were the only thing on the cache line, then a line being in I state meant it was written too, so the SC operation should not store value to x. However, if there were other things on the cache line, it seems that we need to load the line back into our cache to check if that address was actually written to. Maybe we need to use a similar technique to avoiding false-sharing so that a line in I state definitely means x was written to.

I think the states are for each cache line. So if x's state was I, that means x was definitely written to.