So, usually, how many buses are there for the 8GB/16GB system?

I thought it was interesting how there are so many layers of abstraction in all components of the system. For much of this class, we have discussed how pipelining instructions can hide memory access latency, but sort of assume that the memory access itself is simple reading bytes from a large array (the abstraction). But if we look deeper, there are actually interesting things the memory controller can do to further speed up memory requests, such as making use of multiple banks to pipeline the requests. I am interested in knowing if this is something that an application programmer can exploit, or if all of this is handled by the memory controller.

From my understanding, there are some parallels between DRAM and instruction execution. The CAS step in DRAM is the step where the data pins are used, and it is important for the DRAM to have a high "throughput" with these data pins and not having them idle for too long when they could be sending data over. Similarly, it is important to have high throughput during instruction execution as to not have the processor idle for too long. In addition, banking is used in DRAM to simultaneously execute different stages of the pipeline just as different stages of a four-stage instruction pipeline can be simultaneously executed on a processor. However, for DRAM to do so, it must duplicate resources at the level of the bank while for a processor, I'm not sure but I think it just has the four different units for the different stages?