As you can see in the last two slides, there are latency when loading data from DRAM but latency time can be different according to operations included in loading processes. If the loading includes precharge and row activate, latency time will become larger. Thus, it might be better to figure out when the precharge is executed and how to handle different latnecy.

Optimizing for DRAM locality is important, just as optimizing for cache locality is. If bits can be read from the same DRAW row, the program reduces the time it spends activating rows and precharging.

I think that it is however worth to note that with cache locality, we can expect to reach orders of magnitude improvement in the best case since a cache hit is orders of magnitude faster than a DRAM access, in optimizing DRAM locality, we can only hope to gain a much smaller benefit, since the cost of precharging/activating a row is only about 2/3 of the total time.