Is 8 bits of data pins to the memory controller per bank a common hardware setup for DRAM? My initial thought was that a way to improve bandwidth could be to simply increase the number of pins between each bank and the controller. Is the reason people don't do this a chip space or a utilization issue?

Not sure if this is important but what is the purpose of the rows? Can only one column be accessed at once or something?

@trip Increasing the bits to 16 would waste space since the minimal unit of data storage would be 16 bits. You can argue that cache stays at 8 bits but the complexity will go up.

@chii The whole row shares the same precharge circuit. It's too expensive in terms of circuit area to have this circuit per column.

Does anyone know of a good resource to learn more of the implementation details of DRAM? How does the controller select a particular row for the precharge step?

@gpu I find wikipedia explanation is detailed enough for DRAM https://en.wikipedia.org/wiki/Dynamic_random-access_memory#Principles_of_operation. If you take a close look at the graph, it uses demux (demultiplexer) for row selection. The important idea is DRAM takes much less circuit area, only one capacitor and one transistor, compared to SRAM 6 transistors. The capacitor stores the charge and slowly discharges so DRAM needs to be recharged regularly.

What is the major benefit of DRAM over SRAM, since DRAM is usually slower than SRAM? Also is modern computer primarily using DRAM or SRAM?

@wanze Both DRAM and SRAM are used but for different applications: DRAM is slower, but it has the advantage of being denser(higher capacity) hence it is used for main memory. Caches are implemented using SRAM which is faster than DRAM but the trade of is that it's smaller and more expensive hence all the discussions on how to write programs that use data that fits in the cache.