The SMs are laid out in a grid here, and chips have a 2D structure. Is this layout useful and exploited in any way, or would be just as fine to have these laid out in a line? I imagine there are probably some factors related to speed of memory...

That's a great question - do you mean like how they are physically laid out on the die? My understanding is that the SMs are grouped together into clusters, based on this paper about V100 https://images.nvidia.com/content/volta-architecture/pdf/volta-architecture-whitepaper.pdf

I'd make a similar guess about sharing access to memory etc., but I'm not 100% sure