I'm curious whether it is possible to automatically generate Darkroom pipelines in a similar way to how Halide schedules can be automatically generated. Specifically, I wonder if it would be possible to similarly parameterize the search space and use a tree search algorithm to automatically tune parameters relevant to FPGA/ASIC instructions. If this is not possible, I'd love to learn more about the differences between FPGA/ASIC and SIMD/multithreading that would make what I described infeasible.
I'm curious whether it is possible to automatically generate Darkroom pipelines in a similar way to how Halide schedules can be automatically generated. Specifically, I wonder if it would be possible to similarly parameterize the search space and use a tree search algorithm to automatically tune parameters relevant to FPGA/ASIC instructions. If this is not possible, I'd love to learn more about the differences between FPGA/ASIC and SIMD/multithreading that would make what I described infeasible.