Cache coherence in general is based on the notion that if the state of any line in any cache changes, all caches need to know about that change, otherwise one or many of the caches may go into an incoherent state.

The snooping protocols we discussed in the previous lecture accomplish this by having processors/caches "yell out" when the state of one of their cache lines changes, broadcasting a message regarding this change to all other processors/caches, which allows all caches to know about these changes and maintain consistency.

Directory-based coherence schemes take a rather different approach and choose to implement a "single source of truth" which is a centralized directory of information on the level of the L3 cache (since this cache is inclusive, it will contain all cache lines contained in all L1/L2 caches on the same chip). Now, anytime that processors want to get exclusive access to a line to be able to write to it, they must send a message to the directory and wait to hear back with the relevant information before proceeding. By forcing all cache line modification operations go through this directory, the directory can "serialize" memory requests and uphold the single writer, multiple reader model. This helps ensure cache coherency across all caches with the added benefit of greatly reduced traffic on the cache communication bus (no more broadcast for every single cache line change action, only a single point to point message between single cache and directory).

Excellent post!

Are directory entries just additional metadata about cache lines stored in the L3 cache? Or is the directory physically distinct from the L3 cache?

Just think about it as additional metadata on the cache line.

How does directory access exactly work?

My motivation for this question is this. If a cache line is in L1, the core must access the directory at the level of L3 to ensure coherence. Caches would be useless if this directory access were as slow as any other access to the level of L3. So the access to the directory must be faster. Maybe a better question would be what are the steps a core takes to access data in the L1 cache?

@I-henken -- if the cache line is in a core's L1 (your setup), the core would incur a cache hit if accessing that address. The directory only needs to be accessed when a core is changing the status of a line in its cache---exactly when a cache miss would have occurred.

Thanks for the fast response! If two core's wanted to change the status of the same cache line in their respective cores, the directory deals with these two requests, thus serializing the requests as @nbowman said above?