L1 cache is usually faster, but smaller and more expensive than L2 and L3 cache. L1 cache needs to be really quick, and so a compromise must be reached, between size and speed. When the CPU runs an operation that requires data in memory, it starts with checking the tag in the lowest cache level. If a cache miss occurs, the CPU tries to find data in the other cache levels.

Is there any method to intentionally reduce the cache miss rate while coding? For example, if use vector structure instead of list, I guess related data are more likely to be stored in the cache.

I wonder the same as @SebL, coming back from the lecture on cache coherence problem which can also be thought of a cache miss problem, I wonder if there are ways we could avoid this during coding.