Because of the amortization, are SIMD-based architectures able to take on more intelligent control logic than the cores from the "Idea #1" slide?

What would be a more accurate summary of SIMD vs. SIMT?

For example, this is one explanation from googling: " In SIMD, multiple data can be processed by a single instruction. In SIMT, multiple threads are processed by a single instruction in lock-step. Each thread executes the same instruction, but possibly on different data. " So does each thread in SIMT require its own execution context while instructions SIMD do not require their own execution context?

With the introduction of SIMD, changes to existing register files were required. What are the tradeoffs between SIMD and area?

I'm a little unclear on the exact behavior of ALUs. I know that we must distribute only one instruction per 8 (in this example) ALUs because we only fetch/decode a single instruction per processor.

However, why are ALUs specific to each processor? Is there a hardware/other explanation for why a processor can't draw from a centralized pool of ALUs and use as many as it needs to complete a SIMD instruction?

https://en.wikipedia.org/wiki/Single_instruction,_multiple_threads Single instruction, multiple thread (SIMT) is an execution model used in parallel computing where single instruction, multiple data (SIMD) is combined with multithreading.

@jlara I think a centralized pool of ALUs would complicate the control logic and add cost to communications. SIMD is a simple approach where the output of the decoder is directly wired to many ALUs in parallel. These ALUs are doing the logic (add, sub, mul...) and the final results are filtered out using a mask and some add gates. Centralized ALUs pools means you need to have separate logic to distribute ALUs, which could be complicated and slow. Besides there would be more long wires which add to communication and energy cost.

@l-henken Extra vector registers are added for SIMD but on registers do not take much area compared to cache.