At step 4, how can P1 read from P3's cache? Does the memory first have to be written back to main memory after step 3 and then accessed by P1?
vikulg
When P1's cache controller issues a BusRd, P3's cache controller issues a BusWB, which P1's cache controller uses to update its own cache. The BusWB that P3's cache controller issues also updates main memory.
In general, I believe a BusWB from one cache controller updates the state and data for the corresponding cache line in all other caches (that contain this line). In other words, if a cache controller receives a BusWB for a cache line in state I, that cache line should move to state S.
At step 4, how can P1 read from P3's cache? Does the memory first have to be written back to main memory after step 3 and then accessed by P1?
When P1's cache controller issues a BusRd, P3's cache controller issues a BusWB, which P1's cache controller uses to update its own cache. The BusWB that P3's cache controller issues also updates main memory.
In general, I believe a BusWB from one cache controller updates the state and data for the corresponding cache line in all other caches (that contain this line). In other words, if a cache controller receives a BusWB for a cache line in state I, that cache line should move to state S.