Can someone help explain the difference between the SIMD quad-core processor and the superscalar dual core processor?
danieltc
I think the difference is as follows:
A superscalar dual core processor has two cores, where each core has 2 fetch/decode units, 2 ALUs, and 1 shared execution context. It exploits ILP by (potentially) executing multiple independent instructions at once e.g. the first two lines in the forall loop. In total, it can run 2 separate instruction streams with superscalar execution, totalling a maximum of 4 instructions per clock.
The SIMD quad-core processor has 4 cores, where each core has one fetch/decide unit, 8 ALUs, and 1 shared execution context. It exploits the fact that the same instruction is being applied to multiple data using 8-wide vector instructions e.g. calculating result[i] for i = 0, ..., 7 at the same time. In total, it can run 4 separate instruction streams, each with 8-wide instructions, totalling a maximum of 32 vector lanes being computed per clock.
Can someone help explain the difference between the SIMD quad-core processor and the superscalar dual core processor?
I think the difference is as follows:
A superscalar dual core processor has two cores, where each core has 2 fetch/decode units, 2 ALUs, and 1 shared execution context. It exploits ILP by (potentially) executing multiple independent instructions at once e.g. the first two lines in the forall loop. In total, it can run 2 separate instruction streams with superscalar execution, totalling a maximum of 4 instructions per clock.
The SIMD quad-core processor has 4 cores, where each core has one fetch/decide unit, 8 ALUs, and 1 shared execution context. It exploits the fact that the same instruction is being applied to multiple data using 8-wide vector instructions e.g. calculating result[i] for i = 0, ..., 7 at the same time. In total, it can run 4 separate instruction streams, each with 8-wide instructions, totalling a maximum of 32 vector lanes being computed per clock.